Floating gate and charge trapping based multi-time programmable (MTP) non-volatile memory (NVM) devices have achieved widespread adoptions in analog and mixed signal ICs due to their CMOS compatibility and low cost. However, current embedded MTP suffers from scaling issue, endurance/retention limit, high power consumption, complex structure, additional processing steps and high cost.
Therefore, it is desirable to provide an area efficient, low power, high speed and highly reliable MTP memory. Furthermore, it is also desirable to provide simplified methods to produce such MTP memory which is compatible with CMOS processing and with reduced manufacturing cost.